VHDL | Adiuvo Engineering

ADIUVO ENGINEERING BLOG

MicroZed Chronicles: Glitch Filtering

Our programmable logic designs are often deployed in applications which can be electrically noisy. This noise can affect the signals that...

MicroZed Chronicles: Getting Started with Cocotb

Verification of both the modules and top-level testing is often more complex and time consuming than creating the HDL. Previously, we’ve...

MicroZed Chronicles: 10 Rules for HDL Development.

Writing good, portable, reusable HDL code, that enables the synthesized design to implement at the desired frequency can definitely be a...

MicroZed Chronicles: MATLAB / Simulink HDL Coder

A couple of weeks ago, I mentioned I had invested in MATLAB and HDL Coder to enable generation of RTL code directly from Simulink models....

MicroZed Chronicles: Using a DSP48E2 as a Multiplexer

I am a regular reader of many FPGA notice boards. A few days ago, I saw a question about how the DSP48E2 could be used as a multiplexer....

MicroZed Chronicles: MicroBlaze in Spartan-6 (ISE/EDK) and 7 Series (Vivado)

Over the years, I have created MicroBlaze solutions for many Xilinx devices including Spartan-6, 7 series and up. Inserting a MicroBlaze...

MicroZed Chronicles: GitHub Copilot

Programable logic is, of course, great for the implementation and acceleration of machine learning and artificial intelligence...

MicroZed Chronicles: GHDL and UVVM Framework

In this post, we will expand the use of GHDL with an open-source verification framework for VHDL called UVVM.